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Espressif Systems /ESP32-P4 /MIPI_DSI_BRIDGE /DMA_FRAME_INTERVAL

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Interpret as DMA_FRAME_INTERVAL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMA_FRAME_SLOT0DMA_FRAME_INTERVAL0 (DMA_MULTIBLK_EN)DMA_MULTIBLK_EN 0 (EN)EN

Description

dsi_bridge dam frame interval control register

Fields

DMA_FRAME_SLOT

this field configures the max frame_slot_cnt
DMA_FRAME_INTERVAL

this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full
DMA_MULTIBLK_EN

this bit configures enable multi-blk transfer, 0: disable, 1: enable
EN

this bit configures enable interval between frame transfer, 0: disable, 1: enable

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data